The present invention relates generally to memory devices, and more particularly, to a system and method for low-latency addressing in a flash memory.
Flash memories, particularly NOR flash memories, are a type of non-volatile semiconductor memories capable of retaining stored data even when power to the memory is turned off. Due to their non-volatile nature, flash memories are used in limited power applications, viz., battery powered mobile phones, personal digital assistants (PDAs), laptops, netbooks, and the like.
A NOR flash memory includes a plurality of sectors of varying sizes, e.g., 4 kilobyte (KB), 64 KB, and 256 KB. Depending on the sector size, the flash memory includes a varying count of memory cells. The design of the NOR flash memory enables individual addressing of each memory cell, which increases access speed to each memory cell. The fast and random-access nature of NOR flash memories renders them ideal for storing operating systems of battery powered devices.
Memory cells of a conventional NOR flash memory may be addressed either serially or in parallel. Serial addressing entails fetching and storing data in plurality of cycles of a serial clock signal. An exemplary serial data fetch sequence is illustrated in FIG. 1.
FIG. 1 is a timing diagram 100 that illustrates a conventional data fetch sequence in a serial NOR flash memory. The timing diagram 100 includes a chip select (CS) signal 102 and a serial clock (SCK) signal 104.
At time t0, the CS signal 102 transitions to an active low state, which indicates the beginning of a data fetch sequence. At time t1, the SCK signal 104 transitions to active low state signaling initiation of an instruction cycle of the serial NOR flash memory. During the instruction cycle, an instruction received from an external processor (not shown) is transmitted to the flash memory by way of a memory controller. Typically, the instruction cycle includes 8 clock cycles of the SCK signal 104 to enable transmission of an 8-bit instruction received from the processor. At time t2, an address cycle is initiated, during which an address of a memory cell to be accessed is provided to the flash memory. A memory cell address includes 32 bits necessitating the address cycle to last for 32 clock cycles of the SCK signal 104. The address bits of a 32-bit memory cell address may be divided into 8 most significant bits (MSBs) that correspond to a sector address of a sector associated with the memory cell and 24 least significant bits (LSBs) that correspond to a sector specific address that is used to locate the memory cell in the sector. During the address cycle, the 8 MSBs and 24 LSBs are transmitted to the flash memory by the memory controller. At time t3, the address cycle ends and a dummy data cycle is initiated that continues until time t4 at which a data cycle is initiated during which data read from the memory cell is output.
Since NOR flash memories provide a reliable and fast access storage environment, they are being increasingly used to implement execute-in-place (XiP) functionality in portable battery powered devices. The XiP functionality entails execution of programs directly from the flash memory rather than executing the programs in the traditional copy and execute mode in which the programs are copied into a random access memory (RAM) followed by their execution.
However, implementing XiP for performance-intensive applications requires the flash memory to execute low-latency data fetch operations. In the above-described data fetch sequence, code stored in non-contiguous memory locations, i.e., in groups of memory cells spread across multiple sectors, slows down the fetch sequence. Since each fetch sequence includes transmission of complete 32-bit memory cell address to the serial flash memory, fetching data from multiple sectors renders the XiP functionality less effective for performance-intensive applications as compared to the traditional copy and execute mode.
Therefore, it would be advantageous to have a system and method for providing an addressing scheme for a serial NOR flash memory that reduces duration of address cycles, reduces latency of the data fetch sequence, and that overcomes the above-mentioned limitations of conventional serial NOR flash memory addressing schemes.